1. Field of the Invention
The invention relates to a clock and data recovery circuit, and more particularly to a jitter-tolerance-enhanced clock and data recovery circuit using a GDCO-based phase detector.
2. Description of the Related Art
Jitter tolerance refers to the maximum amplitude of sinusoidal jitter (as a function of frequency) that can be tolerated without incorrect recovered data. A conventional phase-tracking clock and data recovery (CDR) circuit has a jitter tolerance inversely proportional to the jitter frequency, thus it is necessary to increase the CDR's loop bandwidth by changing the values of loop parameters to accommodate more high-frequency jitter. However, this might increase jitter transfer and may not be accepted in some applications, such as data repeaters. The trade-off between jitter transfer and jitter tolerance narrow the design margin and some non-idealities, such as non-linearity and the sampling offset, make the performance worse. In traditional optical receivers without jitter tolerance enhancement, the high-frequency jitter tolerance is difficult to exceed 0.5 UIpp (unit interval, peak-to-peak, which is 50% of the theoretical value). One of the remedies is to adopt an analog phase shifter such as a DLL into traditional CDRs. The DLL with wider bandwidth absorbs the jitter modulated on the incoming data and allows the main CDR to recover data correctly. This technique is effective; however, the power consumption and chip area increase.